1. Field of the Invention
The invention relates generally to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a CMOS transistor, the process of which is much simpler than that of the dual LDD structure, so that the production yield can be enhanced.
2. Description of the Prior Art
Conventionally, the structure of the CMOS transistor the gate of which is more than 0.3 .mu.m in length, is consisted of an NMOS transistor of a general LDD structure and a PMOS transistor of which a P-channel punch-stop doping region is formed simultaneously when LDD ions are implanted, the sectional view of which is shown in FIG. 1.
Referring now to FIG. 1, the method of manufacturing the CMOS transistor will be described in detail as follows.
A field oxide 102 is formed on a semiconductor substrate 101 to define a first region in which the NMOS transistor will be formed and a second region at which the PMOS transistor. Then, a P-well 103 is formed within the first region of the semiconductor substrate 101 by ion implantation process, and a N-well 104 is formed within the region of the semiconductor substrate 101 by ion implantation process. Thereafter, a gate oxide film 105 and a gate electrode 106 are sequentially formed at a selected region on the first and second regions. Then, low concentration N-type impurities are implanted into the entire structure, thereby forming a low concentration N-type impurity implantation region 107a at the first region of the semiconductor substrate 101, and at the same time forming a P-channel punch stop doping region 107b at the second region of the semiconductor substrate 101. After forming a spacer 108 at the side walls of the gate electrode 106 and the gate oxide film 105, high concentration N-type impurities are implanted to form high concentration N-type impurity implantation region 109a on the semiconductor substrate 101 of the first region, and high concentration P-type impurities are implanted to form high concentration P-type impurity implantation region 109b on the semiconductor substrate 101 of the second region.
In this transistor structure, in case that the NMOS transistor has the gate length of less than 0.3 .mu.m, the junction depth of low concentration impurity implantation region must be made less than 0.12 .mu.m and at the same time the doping concentration of the low concentration impurity implantation region must be lowered in order to prevent the short channel effect.
Meanwhile, in order to form this ultra shallow low concentration impurity implantation region, it is required that the much lower ion implantation energy has to be used than that used in the prior art. However, in case that such a low energy and low concentration ion implantation are used, there is a problem that the punch-through characteristic is greatly deteriorated to cause a problem in a device having the tage length of less than 0.35 .mu.m, since the N-type impurity concentration and diffusion length of the buried channel region of the PMOS transistor are low.
Referring now to FIG. 2, there is shown a conventional method for solving the above-mentioned problems. The method as shown in FIG. 2 is related to a method of forming a CMOS transistor having an ultra shallow dual structure of N-LDD and P-LDD structure, and is capable of forming a transistor having the gate length of less than 0.1 .mu.m. The method shown in FIG. 2 forms punch stop doping regions 210a, 210b below the low concentration impurity implantation region 107a and 107b in the structure shown in FIG. 1. However, as this method requires two times ion implantation mask process for forming the dual LDD, and also a punch stop ion implantation process for making two times large inclination, there are problems that it makes the entire processes more complicated and lowers the production yield.